Tesla Unveils Revised SI Accelerator Roadmap: AI4, AI5 and AI6 Renamed SI4, SI5 and SI6, Sixth-Generation SI6 Inference Chip Targets 80 Times the Compute and Nine Times the Memory of the Current Chip, Dojo D3 Moves to Chiplets With Stacked HBM
Tesla has disclosed a revised artificial-intelligence accelerator roadmap and renamed its chip line, according to a November 6 report by Tom's Hardware based on Tesla presentation materials. The three generations of inference chips previously called AI4, AI5 and AI6 are now labeled SI4, SI5 and SI6, under what the report describes as a "super intelligence" branding push.
The headline figure in the roadmap concerns the sixth-generation inference accelerator, the SI6. Per Tesla's presentation, the SI6 is expected to deliver about 80 times the compute performance of the existing fourth-generation chip, and about nine times the memory. Tesla does not publish the current chip's absolute compute performance, so absolute performance ranges circulating in coverage are estimates derived from an estimated baseline, not figures Tesla has officially disclosed.
On the training side, the roadmap shows the next Dojo training accelerator, D3 (Dojo 3), dropping its earlier SRAM-centric architecture in favour of a multi-chiplet design with stacked high-bandwidth memory (HBM). Tesla has not disclosed D3's compute performance, memory capacity, manufacturing process or launch schedule, according to the report.
Tom's Hardware said the roadmap sheds light on the future of Tesla's in-house chip development: inference continues along the SI series, while training restarts on an entirely new D3 architecture. The performance targets and timing in the presentation are Tesla's stated plans, not measured results from production hardware.
Source: Tom's Hardware
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